Mechanisms Hiding Miss Penalty for Cache Memory to Shared Variables with Synchronization on a Chip-multiprocessor
| Accession number;06A0116179 |
| Title;Mechanisms Hiding Miss Penalty for Cache Memory to Shared Variables with Synchronization on a Chip-multiprocessor |
| Author;YAMAWAKI AKIRA(Kyushu Inst. Technol., Faculty of Engineering, JPN) IWANE MASAHIKO(Kyushu Inst. Technol., Faculty of Engineering, JPN) |
Journal Title;Transactions of Information Processing Society of Japan
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Journal Code:Z0778A
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ISSN:0387-5806
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VOL.47;NO.2;PAGE.566-581(2006)
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| Figure&Table&Reference;FIG.22, TBL.10, REF.21 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;To hide cache miss penalty is important for improving a performance of processors. On a chip-multiprocessor, the TSVM cache performs inter-processor communication and synchronization simultaneously with coherence maintenance to make parallel processing more efficiently. To utilize entries more efficiently among tasks and threads, the TSVM cache specifies a shared variable with synchronization by the tag including the task ID and thread ID. To not use a structured physical memory with synchronization mechanism, the TSVM cache treats shared variables with synchronization as just structures on a conventional main memory. Thus, when a cache miss occurs, the TSVM cache translates a tag to the address and transfers the structured line to the memory. This paper attempts to improve the performance more by introducing the mechanisms to hide the miss penalty for the TSVM cache. The result shows that the introduced mechanisms improve a speedup up to 2.77 times (1.91 times on average) compared with a conventional data cache, and suppress a bus utilization up to 17% (11% on average). It is also confirmed that overheads of communication and synchronization make a capability of prefetching delay strong. (author abst.) |
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